Level shifters transfer signals between different domains. Typically, these domains operate under different voltage ranges. A level shifter transfers a signal generated from an integrated circuit operated under one voltage domain to an integrated circuit operated under another voltage domain.
FIG. 1a is illustrates a schematic of a conventional level shifter 100. It comprises cross-coupled PFETs 110 and 120 which are coupled to pull-down NFETs 160 and 150 respectively. FIG. 1b illustrates the relevant waveforms at some of the nodes. When input d is low, inverter 170 forces db to be high, thereby turning “OFF” NFET 150 while turning “ON” NFET 160. Since NFET 160 is “ON,” the gate of the PFET 120 is pulled low, thereby pulling the drain of PFET 120 (node n1) high. Node n1 drives the output q of the inverter, comprising PFET 130 and NFET 140, to low. Subsequently, when d transitions to high, db is forced low by the inverter 170. Node n1 is pulled low by NFET 150, resulting in output q going high and PFET 110 being turned “ON”. This pulls node n2 high, turning “OFF” PFET 120.
The drawback with configuration 100 is that it suffers from transition delay between the d input and the q output as well as from excessive power consumption. For example, when the d input transitions to high, there is contention between NFET 150 and PFET 120. During this transition phase, a shoot-through current goes from Vdd through PFET 120 and NFET 150 to Vss, resulting in substantial power loss. Curve 188 of FIG. 1b illustrates the integral of the current consumption, assuming a Vdd of 5V. Further, the contention between PFET 120 and NFET 150 (i.e., during a transition phase) contributes to the propagation delay between input d and output q. As node n1 is pulled low, PFET 110 is slowly turned “ON,” which in turn gradually switches PFET 120 “OFF.” The current in PFET 120, while NFET 150 is fighting with PFET 120 to bring node n1 to “LOW,” is not usefully employed to discharge node n1. Accordingly, the propagation delay from node d going high to output q going low, increases.
FIG. 2 illustrates a schematic of an improved prior art level shifter 200. Level shifter 200 is similar to level shifter 100 except that it includes additional PFETs 255 and 265. The contention problem is alleviated because during transitions, PFET 220 and NFET 250 are both “ON” at the same time, while PFET 255, between the drains of PFET 220 and NFET 250, is turned “OFF.” Similarly, contention between PFET 210 and NFET 260 is also avoided by PFET 265. Since contention during transition periods is reduced (i.e., there is no direct path between Vdd and Vss), shoot-through currents from Vdd to Vss are avoided. For example, when d goes high, PFET 255 is turned “OFF” while PFET 265 is turned “ON.” PFET 220, which is in series with PFET 255, is turned “OFF” by the resulting high at node n2 (at the gate of PFET 220). Accordingly, the series connection of PFET 220 and PFET 255 prevents any current flow from Vdd through NFET 250 to Vss.
Level shifter 200 of FIG. 2, however, has the drawback of only avoiding contention between the respective PFETs and NFETs when the supply voltages are low enough to allow PFETS 255 and 265 to be turned “OFF” and “ON” effectively. For example, assuming that PFET 255 has a threshold of 1V, if the gate voltage of PFET 255 goes to 2.5V, representing a logic high at input d, PFET 255 can only be effectively turned “OFF” with a Vdd voltage of 3.5V or lower. Thus, with a Vdd voltage of 5V, PFET 255 cannot be turned “OFF” effectively. In this regard, a contention between PFET 220 and NFET 220 during transition periods is not prevented.
It is therefore a goal of an embodiment of the present invention to provide a level shift circuit and method with faster propagation times and less power consumption.